Senior FPGA Developer

Senior FPGA Developer

Location: Islamabad

Company: Teresol Pvt. Ltd.

Experience Required: 3+ Years

TeReSol (Pvt.) Ltd. is seeking an experienced and motivated Senior FPGA Developer to join our Hardware Engineering team. This role is ideal for professionals with strong expertise in FPGA development, RTL design, verification, and system integration on AMD Zynq platforms. The selected candidate will contribute to complex hardware solutions while mentoring junior engineers and driving technical excellence.

Role Overview:

As a Senior FPGA Developer, you will independently lead RTL development, verification, timing closure, and FPGA integration activities across advanced hardware projects. You will work closely with software, systems, and hardware teams to deliver high-performance FPGA-based solutions.

Key Responsibilities:

• Develop and review RTL designs using Verilog, VHDL, and SystemVerilog for AMD Zynq platforms.

• Design and maintain simulation testbenches for functional verification and coverage.

• Perform functional and timing simulations and resolve timing closure challenges.

• Port and migrate RTL designs across FPGA device families.

• Conduct hardware bring-up, debugging, and validation activities.

• Prepare technical documentation including architecture diagrams, simulation reports, and optimization summaries.

• Lead IP integration activities using Vivado IP Integrator (IPI).

• Optimize design performance and FPGA resource utilization.

• Review and mentor junior engineers on RTL and verification practices.

• Collaborate with cross-functional engineering teams throughout the development lifecycle.

Technical Requirements:

Core FPGA & Digital Design:

• Hands-on experience with AMD Zynq-7000 or Zynq UltraScale+ SoC/MPSoC platforms.

• Strong proficiency in Verilog, VHDL, or SystemVerilog.

• Solid understanding of digital design concepts including FSMs, pipelining, and clock-domain crossing.

• Experience in simulation and verification methodologies (UVM is a plus).

• Strong knowledge of timing analysis, setup/hold constraints, and timing closure techniques.

• Experience with AXI4, AXI4-Lite, AXI4-Stream protocols and Zynq PS–PL interfacing.

• Familiarity with AMD/Xilinx IP cores including DMA, AXI Interconnect, MIG, and FIFO.

• Experience integrating custom RTL IP into Vivado block designs.

• Working knowledge of Vitis and Petalinux environments.

• Experience with advanced Vivado capabilities such as debug insertion, hierarchical design, and partial reconfiguration.

Additional Skills:

• Experience with Git and collaborative development workflows.

• Strong technical documentation and communication skills.

• Ability to independently manage priorities and meet project milestones.

Education:

Bachelor’s/Master’s degree (B.Sc., B.E., M.Sc., or M.E.) in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.

Apply at: hr@teresol.com